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| 1. general description the greenchip is the latest generation of green switched mode power supply (smps) controller ics. the TEA1755T combines a controller for power factor correction (pfc) and a flyback controller. its high level of integration enables cost-effective power supply design using a very low number of external components. the pfc operates in quasi-resonant (qr) or discontinuous conduction mode (dcm), with valley switching. the specially built-in green fu nctions provide high efficiency at all power levels. at high power levels the flyback operates in qr mo de or dcm with valley detection. at medium power levels, the flyback controller switches to frequency reduction (fr) mode and limits the peak current to an adjustable minimum value. in low power mode, the pfc switches off to maintain high efficiency. at very low power levels, when the flyback switching frequency drops below 25 khz, the flyback converter switches to burst mode. during the non-switching phase of burst mode, the internal ic supply current is minimized to further optimize efficiency. valley switchi ng is used in all operating modes. the advanced burst mode ensures high-efficiency at low power and good standby power performance while minimizing audible transformer noise. the TEA1755T is a multi-chip module, (mcm), containing two chips. the proprietary high-voltage bcd800 process makes direct start- up possible from the rectified universal mains voltage in an effective and green way. the second low volta ge silicon-on-insulator (soi) is used for accurate, high-speed protection functions and control. the TEA1755T enables easy design of highly efficient and reliable supplies up to 250 w. these power supply designs are cost-effective , requiring the minimum number of external components. remark: all values in this document are typical values unless otherwise stated. TEA1755T hv start-up dcm/qr flyback c ontroller with integrated dcm/qr pfc controller rev. 1 ? 25 october 2012 product data sheet
TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 2 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 2. features and benefits 2.1 distinctive features ? integrated pfc and flyback controller ? universal mains supply operat ion between 70 v (ac) to 276 v (ac) ? dual-boost pfc with accurate maximum output voltage (nxp semiconductors patented) ? high level of integration, re sults in cost-effective designs with very low external component counts ? adjustable pfc switch off delay ? external pfc switch on and switch off override ? accurate pfc switch on and switch off control (nxp semiconductors patent pending) 2.2 green features ? on-chip start-up current source ? reduced ic supply current during burst mode enabling erp lot 6 ? power-down functionality for very low standby power 2.3 pfc green features ? valley/zero-voltage switching (zvs) for minimum switching losses (nxp semiconductors patented) ? frequency limitation re duces switching losses ? pfc switched off when a low-load is detected at the flyback output 2.4 flyback green features ? valley switching for minimum switching losses (nxp semiconductors patented) ? frequency reduction with adjustable minimu m peak current at low-power operation maintains high-efficiency at low output power levels ? burst mode operation at very low-power levels for high-efficiency operation 2.5 protection features ? safe restart mode for system fault conditions ? continuous mode protection using demagn etization detection for both converters (nxp semiconductors patented) ? undervoltage protection (uvp) (foldback during overload) ? accurate overvoltage protection (ovp) for both converters (adjustable for flyback converter) ? mains voltage independent overpower protection (opp) ? open control loop protection for both converters. the open-loop protection on the flyback converter is safe restart ? overtemperature protection (otp) ? low and adjustable overcurrent protection (ocp) trip level for both converters ? general-purpose input for latched protection, for use with system overtemperature protection (otp) TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 3 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 3. applications ? the device can be used in all applications requiring an efficient and cost-effective power supply solution for up to 250 w. notebook adapters in particular benefit from the high level of integration 4. ordering information 5. block diagram table 1. ordering information type number package name description version TEA1755T/1 so16 plastic small outline packa ge; 16 leads; body width 3.9 mm sot109-1 fig 1. TEA1755T block diagram timer 48 s timer 4.2 s pfc protection v o ovp v th(vosense) t on reduction near ovp ocp pfc driver enable pfc start stop pfc 495 mv pfc gate valley detect blank 3.32 v 2.5 v 1.92 v maximum external protection protection external protection v startup charge control safe restart protection start flyback start stop pfc protection v cc good charge pfc protection protection latch reset enable pfc r s q low power delay burst mode v th(burst) pfc clamp smps control v cc good start soft start flyback enable flyback enable flyback blank q r s flyback oscillator t on(max) frequency reduction external protection time-out burst mode flyback driver flyback gate 12 13 pfc driver pfc gate vinsense pfccomp vosense pfcsense pfcaux otp charge valley detect otp internal supply zero current signal zero current signal flyback gate fbaux fbsense counter ovp ovp flyback 3.5 v 7 6 11 8 9 hv v cc 16 1 gnd 5 3 10 4 fbctrl latch 90 mv pfcdriver fbdriver v startup v th(uvlo) v th(uvlo) aaa-002622 protection pfc(swon) pfc(swoff) control 30.5 a 60 a 29 a 3.75 v clamp ocp frequency reduction burst mode 494 v v th(burst) flyback driver 5.5 v 7.0 v temperature -90 mv 8.1 a dual boost dual boost dual boost low vin power down ton max power down power down opp opp opp minimum 2 low power delay low power pfctimer 14 delay 60 a 2.1 a ovp flyback external protection otp latch reset s s s r latched protection pfc clamp clamp soft start soft stop v en(pfc)fbctrl low power delay time-out r s s s v th(vosense) low vin v uvlo driver driver pfc oscillator low power v en(pfc)fbctrl TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 4 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 6. pinning information 6.1 pinning 6.2 pin description fig 2. TEA1755T pin configuration (sot109-1) table 2. pin description symbol pin description v cc 1 supply voltage gnd 2 ground fbctrl 3 flyback control input fbaux 4 auxiliary winding input for demagnetization timing and flyback ovp latch 5 general-purpose protection input pfccomp 6 pfc frequency compensation vinsense 7 mains voltage sense input pfcaux 8 auxiliary winding input for demagnetization timing of the pfc vosense 9 sense input for pfc output voltage fbsense 10 flyback current sense input pfcsense 11 pfc current sense input pfcdriver 12 pfc gate-driver output fbdriver 13 flyback gate-driver output pfctimer 14 pfc override and switch off delay timer hvs 15 high-voltage safety spacer; not connected hv 16 high-voltage start-up and flyback valley sensing TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 5 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7. functional description 7.1 general control the TEA1755T contains a power factor correc tion circuit controller and a flyback circuit controller. a typical conf iguration is shown in figure 3 . 7.1.1 start-up and undervoltage lockout (uvlo) initially, the capacitor on the v cc pin is charged from the high-voltage mains using the hv pin. when v cc is less than v trip , the charge current is i ch(low) . this low current protects the ic if the v cc pin is shorted to ground. to ensure a s hort start-up time, the charge current above the v trip level is increased to i ch(high) , until v cc reaches v th(uvlo) . when v cc is between v th(uvlo) and v startup , the charge current goes low again to ensure a low safe restart duty cycle during fault conditions. the control logic activates the internal circui try and switches off the hv charge current when v cc passes the v startup level. first, the latch pin cu rrent source is activated and the soft-start capacitors on the pfcsense and fbsense pins are charged. also the clamp circuit on the pfccomp pin is activated. the pfc circuit is activated when the following conditions are met: (1) the hv pin can either be connected to the center tap of the flyback transformer or to the drain of mosfet s2. fig 3. a typical TEA1755T configuration 12 11 9 16 13 8 6 7 3 214 gnd latch v cc fbaux fbsense pfcdriver fbdriver pfcsense vosense hv pfcaux pfccomp vinsense fbctrl 10 4 1 5 pfctimer ic aaa-002624 tr2 d4 d3 c5 (1) c pfctimer r ntc c vcc s2 d 2 r4 r comp r s1 r5 s1 c ss1 r ss1 r sense1 r drv2 r drv1 r s2 r ss2 r s3 r sense2 r fbaux c ss2 c6 c bulk v out z1 tr1 r aux1 v mains c1 d1 r1 r2 r loop c timeout opto-feedback opto- feedback r3 c2 c4 c3 TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 6 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers ? the latch pin voltage exceeds the v en(latch) voltage ? the pfccomp pin charging current drops below the absolute value of the i en(pfccomp) current ? the soft-start capacitor on the pfcsense pin is charged the flyback converter is also activated if th e soft-start capacitor on the fbsense pin is charged. the flyback converter output voltage is then regulated to its nominal output voltage. the auxiliary winding of the flyba ck converter takes over the ic supply. see figure 4 . if during start-up, the latch pin does not reach the v en(latch) level before v cc reaches v th(uvlo) , the latch pin output is deactivated. th e charge current is switched on again. when the flyback converter is started, v fbctrl is monitored. if the output voltage does not reach its intended regulation le vel within a specified time, v fbctrl reaches the v to(fbctrl) level. an error is then assumed and a safe restart is initiated. when one of the safe restart or latched protec tion functions are triggered, both converters stop switching and the v cc voltage drops to v th(uvlo) . a latched protection recharges capacitor c vcc using the hv pin, but does not restart the converters. to provide safe restart protection, the capacitor is recharged using the hv pin and the device restarts (see block diagram, figure 1 ). if ovp is triggered on the pfc circuit (v vosense >v ovp(vosense) ), the pfc controller stops switching until the v vosense < v ovp(vosense) . if a mains uvp is detected, v vinsense TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 7 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.1.2 power-down mode the power-down mode can be activated for very low standby power applications by pulling the v vinsense < v th(pd) level. the TEA1755T stops switching and safe restart protection is activated. the high voltage star t-up current source is also disabled during power-down and the TEA1755T does not restart until v vinsense is raised again. during power-down mode, all internal circuitry is disabled except for a voltage detection circuit on the vinsense pin. this circuit is supplied by the hv pin and draws 12 ? a from the hv pin for biasing. fig 4. start-up sequence, normal operation and restart sequence v cc latch protection pfcsense pfcdriver fbsense fbdriver fbctrl vosense v o charging vcc capacitor starting converters normal operation protection restart soft start soft start i hv v start(vinsense) v to(fbctrl) v startup v th(uvlo) v trip v en(la tch) v start(fb) vinsense 014aaa744 pfccomp v en(pfccomp) TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 8 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.1.3 supply management all internal reference voltages are derived from a temperature compensated and trimmed on-chip band gap circuit. internal reference currents are derived from a temperature compensated and trimmed on-chip current reference circuit. 7.1.4 latch input the latch pin is a general-purpose input pin wh ich is used to switch off both converters. the pin sources a current i o(latch) of 30.5 ? a. switching of both converters is stopped when v latch is < 494 mv. at initial start-up, switching is prevented until the capacitor on the latch pin is charged above 582 mv. no internal filtering is performed on this pin. an internal 1.75 v clamp protects the pin from excessive voltages. 7.1.5 fast latch reset in a typical application, the mains can be interrupted briefly to reset the latched protection. the bulk capacitor c bulk does not have to discharge for th is latched protection to reset. when the vinsense voltage drops below 750 mv and is then raised to 860 mv, the latched protection is reset. the latched protection is also reset by removing both the voltage on the v cc and hv pins. 7.1.6 overtemperature protection an accurate internal temperature protection is provided in the ic. when the junction temperature exceeds the thermal shut-down te mperature, the ic stop s switching. while otp is active, the capacitor c vcc is not recharged from the hv mains. if the v cc supply voltage is not sufficient, the otp circuit is supplied from the hv pin. otp is a latched protection. it is reset by removing the voltage from both the v cc and hv pins or by the fast latch reset function (see section 7.1.5 ). 7.2 power factor correction circuit the power factor correction (pfc) circuit operates in quasi-resonant (qr) or discontinuous conduction mode (dcm) with valley switching. the next primary stroke is only started when the previous secondary stroke has ended and the voltage across the pfc mosfet has reached the minimum value. v pfcaux is used to detect transformer demagn etization and the minimum voltage across the external pfc mosfet switch. 7.2.1 t on control (pfccomp pin) the power factor correction circuit is operated in t on control. the resulting mains harmonic reduction is well within t he class-d requirements. v pfccomp determines the on-time of the pfc. the v vosense is the transconductance amplifier input which outputs current to the pfccomp pin. the regulation v vosense = 2.5 v. the network connected to the pfccomp pin and the transconductance amplifier determine the dynamic behavior of the pfc control. TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 9 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers operating near the pfc ovp level causes the pfc stage on-time to decrease rapidly to zero. to reduce the response time, in case of load variation, the pfccomp pin is clamped to a minimum level of 2 v during pfc operation. clamping prevents the on-time increasing too much and improves the pfc response time when the load decreases again. 7.2.2 valley switching and demagnetization (pfcaux pin) the pfc mosfet is switched on after the trans former is demagnetized. internal circuitry connected to the pfcaux pin detects the end of the secondary stroke. it also detects the voltage across the pfc mosfet. to reduce switching losses and electromagnetic interference (emi), the next stroke is started when the voltage across the pfc mosfet is at its minimum (valley switching). if a demagnetization signal is not detected on the pfcaux pin, the controller generates a zero-current signal (zcs) 48 ? s after the last pfc mosfet gate signal. if valley signal is not detected on the pfcaux pin, the controller generates a valley signal 4.2 ? s after demagnetization is detected. to protect the internal circuitry during , for example, lightning events, add a 5 k ? series resistor to the pfcaux pin. to prevent inco rrect switching due to external interference, place the resistor close to the ic on the pcb. 7.2.3 frequency limitation to optimize the transformer and minimize s witching losses, the s witching frequency is limited to f sw(pfc)max . if the frequency for quasi-res onant operation is above the f sw(pfc)max limit, the system switches to dcm. the pfc mosfet is only switched on at a minimum voltage across the switch (valley switching). 7.2.4 mains voltage compensation (vinsense pin) the equation for the transfer function of a power factor corrector contains the square of the mains input voltage. in a typical applicat ion, this results in a low bandwidth for low mains input voltages. at high mains input voltages, the mains ha rmonic reduction (mhr) requirements are hard to meet. to compensate for the influence of the mains input voltage, the TEA1755T contains a correction circuit. the average input volt age is measured using the vinsense pin and the information is fed to an internal compen sation circuit. using this compensation, it is possible to keep the regulation loop bandwidth constant over the mains input range. this feature gives a fast transient response on load steps while still complying with class-d mhr requirements. in a typical application, a resistor and two capacitors connected to the pfccomp pin set the regulation loop bandwidth. 7.2.5 soft-start (pfcsense pin) to prevent audible transformer noise at start-up or during hiccup, the soft-start function slowly increases the transformer peak current. place a capacitor c ss1 in parallel with resistor r ss1 (see figure 5 ) to implement a soft-start func tion. an internal current source charges the capacitor to: TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 10 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers (1) the voltage is limited to v start(soft)pfc . the start level and time constant of the incr easing primary current level is externally adjusted by changing the r ss1 and c ss1 values. (2) the charging current i start(soft)pfc flows while the pfcsense pin voltage is < 0.5 v. if v pfcsense exceeds 0.5 v, the soft-start current source starts limiting current i start(soft)pfc . when the pfc starts switching, the i start(soft)pfc current source is switched off; see figure 5 . 7.2.6 pfc switch on/switch off control when the flyback converter output power (see section 7.3 ) is low, the flyback converter switches to fr mode. when the switching frequency of the flyback in fr mode < f sw(fb)swoff(pfc) (53 khz), the pfc circuit is switched off to maintain high efficiency. connect a capacitor to the pfctimer pin (see section 7.2.7 ) to delay the pfc switching off. during low-power mode operation, the pfccomp pin is clamped to a minimum voltage of 3.32 v or 1.92 v and a maximum voltage of 3.75 v. the lower clamp voltage depends on v vinsense . this voltage limits the maximum power that is delivered when the pfc is switched on again. the upper clamp voltage ensures that the pfc returns from low-power mode to its normal regulati on point in a limited time. in fr mode, when the flyback co nverter switching frequency exceeds f sw(fb)swon(pfc) (73 khz), the pfc circuit is switched on . if the flyback converter duty cycle is > 50 % or v fbctrl is > 3.75 v, the pfc circuit is also switched on. 7.2.7 pfc switch off delay (pfctimer pin) when the flyback converter switching frequency in fr mode is < f sw(fb)swoff(pfc) (53 khz), the ic then outputs a 4.7 ? a current to the pfctimer pin. when v pfctimer reaches 3 v, the pfc is switched off by performing a soft-stop. fig 5. soft-start of the pfc v pfcsense i start soft ?? pfc r ss1 ? = ? soft s ? tart 3 r ss1 c ss1 ?? = soft-start soft-stop control ocp 11 pfcsense 495 mv i start(soft)pfc 60 a s1 r ss1 c ss1 r sense1 014aaa756 TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 11 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers a switch discharges the pfctimer pin capa citor when the flyback controller operating frequency is > f sw(fb)swon(pfc) (73 khz). at the same moment, the pfc stage is also switched on. connect a capacitor to the pfctimer pin (see section 7.2.7 ) to prevent the pfc from switching off due to a dynamic load that leads to repetitive crossing of f sw(fb)swoff(pfc) and f sw(fb)swon(pfc) . a 1 nf minimum capacitor value is recommended to prevent noise influencing the pfc switch on/ switch off behavior. the pfctimer pin capacitor is also discharged when the flyback maximum switching frequency is higher than 53 khz. this feature prevents pfc on/off toggling during dynamic loads causing the flyback to operate repetitively near f sw(fb)swoff(pfc) and f sw(fb)swon(pfc) . it is also possible to control pfc swit ch-on and switch off externally. when v pfctimer is driven below 1.03 v, the pfc stage is on. when the pfctimer pin voltage is driven above 4.4 v, the pfc stage is switched off. the external control overrides the pfc stage control by the flyback controller (see figure 6 ). the pfctimer pin has an internal clamp circuit starting around 10 v with a current capability of 0.1 ma 7.2.8 dual-boost pfc the mains input voltage modulates the pfc output voltage. the mains input voltage is measured using the vinsense pin. if v vinsense < 2.28 v, the current is sourced from the vosense pin. to ensure switch-over is stable, the current reaches its absolute maximum value for v vinsense < 2.08 v, see figure 7 . at low vinsense input voltages, the output current is 8.1 ? a. this output current, in combination with the resistors on the vosense pin, sets the lower pfc output voltage level at low mains voltages. at high mains input voltages, the current is swit ched to zero. the pfc output voltage is then at its maximum. as this current is zero in this situation, it does not affect the accuracy of the pfc output voltage. to ensure a correct switch-off of the app lication, the vosense current switches to its maximum value of 8.1 ? a when v vosense drops below 2.1 v. fig 6. pfc switch on and switch off using the pfctimer pin aaa-002670 4.7 a low power r s q 1.03 v 3 v 14 pfctimer 4.4 v r s q 5.5 k low power delay (pfc on) TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 12 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.2.9 overcurrent protection (pfcsense pin) the maximum peak current is limited cycle-by-c ycle by sensing the voltage across an external sense resistor, r sense1 , on the source of the external mosfet. the voltage is measured using the pfcsense pin. 7.2.10 mains undervoltage lockout/brownout protection (vinsense pin) to prevent the pfc from operating at very low mains input voltages, v vinsense is sensed continuously. when v vinsense drops below the v stop(vinsense) level, switching of the pfc is stopped. 7.2.11 overvoltage protection (vosense pin) to prevent output overvoltage during load steps and mains transients, an overvoltage protection circuit is built in. when v vosense exceeds the v ovp(vosense) level, switching of the pfc circuit is prevented. switching of the pfc restarts when the vosense pin voltage drops below the v ovp(vosense) level again. ovp is also triggered when the resistor between the vosense pin and ground is open. 7.2.12 pfc open-loop protection (vosense pin) the pfc circuit does not start switching until the v vosense pin is greater than the v th(ol)(vosense) level. this feature protects the application from open-loop and vosense short-circuit situations. 7.2.13 driver (pfcdriver pin) the driver circuit to the gate of the power mosfet has a current so urcing capability of 500 ma at 2 v on the pfcdriver pin and a curr ent sink capability of 1.2 a at 10 v on the pfcdriver pin. these capabilities ensure fa st switch-on and swit ch-off of the power mosfet for efficient operation. 7.3 flyback controller the TEA1755T includes a controller for a flyback converter. the flyback converter operates in quasi-resonant, discontinuous conduction mode or burst mode with valley switching. the auxiliary winding of the fl yback transformer provides demagnetization detection and powers the ic after start-up. fig 7. voltage to current transfer function for dual-boost pfc aaa-004486 -8.1 a 2.08 v 2.28 v v vinsense i i(vosense) TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 13 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.3.1 multimode operation the TEA1755T flyback controller can operate in several modes; see figure 8 . at high output power the co nverter switches to quasi-resonant mode. the next converter stroke starts after demagnetization of the transformer and detection of the valley. in quasi-resonant mode switching losses are minimi zed. this minimization is achieved by the converter only switching on when the voltag e across the external mosfet is at its minimum (see section 7.3.2 ). valley switching is active in all operating modes. to prevent high frequency operation at lower loads, the quasi-resona nt operation switches to discontinuous mode operation with valley skipping. when the frequency limit is reached, the quasi-resonant operation changes to dcm with valley skipping. the frequency limit reduces the mosfet switch-on losses and conducted emi. at medium power levels, the controller enters frequency reduction (fr) mode. a voltage controlled oscillato r (vco) controls the fr equency. the mini mum frequency in this mode is reduced to approximately 25 khz. during frequency reduction mode, the primary peak current is kept at an adjustable minimal level to maintain a high efficiency. valley switching is also active in this mode. at very low power and standby levels, for wh ich the switching frequency would drop below 25 khz, the converter enters the burst mode. in burst mode, the switching frequency is 36.5 khz. the primary peak current is fixed in burst mode. in frequency reduction mode, the pfc controller switches off as soon as the flyback switching frequency drops below 53 khz. the flyback maximum frequency changes linearly with the control v fbctrl (see figure 9 ). hysteresis is added to ensure a stable pfc switch-on and switch-off. in no-load opera tion, the switching frequency is reduced to (almost) zero. fig 8. multimode operation flyback discontinuous with valley switching quasi-resonant frequency reduction output power flyback switching frequency aaa-002671 pfc off pfc on 130 khz 73 khz 53 khz 36.5 khz 25 khz i pmin adjust burst mode TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 14 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.3.2 valley switching (hv pin) a new cycle starts when the exte rnal mosfet is switched on. v fbsense and v fbctrl determine the on-time. the mosfet is then switched off and the secondary stroke starts (see figure 10 ). after the secondary stroke, the dr ain voltage shows an oscillation with a frequency of approximately: (3) where l p is the primary self-inductance of the flyback transformer and c d is the capacitance on the drain node. when the secondary stro ke ends and the internal oscilla tor voltage is high again, the circuit waits for the lowest drain voltage before starting a new primary stroke. figure 10 shows the drain voltage, valley signal, se condary stroke signal and the internal oscillator signal. valley switching allows high frequency operat ion because capacitive switching losses are reduced (see equation 4 ). high frequency operation makes small and cost-effective magnetic components possible. (4) fig 9. flyback frequency control aaa-002672 v fbctrl (v) pfc off pfc on flyback switching frequency f sw(fb)max 4.9 4.0 2.82.4 0.77 burst mode frequency fr minimum frequency fr dcm qr bm qr: quasi resonant dcm: discontinuous conduction mode fr: frequency reduction bm: burst mode f 1 2 ?? l p c d ? ?? ? ?? -------------------------------------------------- - = p 1 2 -- - c d v 2 ? f ?? = TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 15 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.3.3 current mode control (fbsense pin) current mode control is used for the flyback converter because of its good line regulation. the fbsense pin senses the primary current acro ss an external resist or and compares it to an internal control voltage. the internal control voltage is proportional to v fbctrl (see figure 11 ). the fbsense pin output s a current of 2.1 ? a. this current runs through the resistors from the fbsense pin to the sense resistor r sense and creates an offset voltage. the minimum flyback peak current is adjusted using this offset voltage. adjusting the minimum peak current level, changes the frequency reduction slope (see figure 8 ). (1) start of a new cycle at lowest drain voltage. (2) start of a new cycle in a classical pulse-widt h modulation (pwm) system without valley detection. fig 10. signals for valley switching drain secondary stroke 014aaa027 secondary ringing primary stroke valley (2) (1) secondary stroke oscillator TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 16 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.3.4 demagnetization (fbaux pin) the system is always in qr or dcm. the internal oscillator does not start a new primary stroke until the previous secondary stroke has ended. demagnetization features a cycl e-by-cycle output short-circuit protection by immediately lowering the frequency (longer off-time) and reducing the power level. demagnetization recognition is suppressed during the first t sup(xfmr_ring) time of 2.2 ? s. this suppression can be necessary at low output voltages, during start-up and in applications where the transformer has a large leakage inductance. if the fbaux pin is open-circuit or not connec ted, a fault condition is assumed and the converter immediately stops. operation rest arts when the fault condition is removed. 7.3.5 flyback control/time-out (fbctrl pin) the fbctrl pin is connected to an internal voltage source of 7 v using an internal 13.2 k ? resistor. when v fbctrl > 5.5 v, the resistor is disconnected. the pin is biased with a 29 ? a current. when v fbctrl > 7.75 v, a fault is assume d, switching is stopped and a restart is made. if a capacitor and resistor are connected in seri es to the pin, a time-out function is created which protects against open control loop situations. see figure 12 and figure 13 . the time-out function is disabled by connecting a resistor (200 k ? ) to ground on the fbctrl pin. if the pin is short-circuited to ground, swit ching of the flyback controller is stopped. under normal operating conditions, the converter regulates the output voltage. v fbctrl varies between 0.77 v at minimum output power and 4.9 v at maximum output power. fig 11. flyback part peak current control v fbctrl (v) 545 mv 232 mv flyback fr mode pfc off pfc on aaa-002673 sense resistor peak voltage fbsense offset voltage v sense(fb)max burst mode 0.77 2.8 4.0 4.9 fbsense peak voltage flyback dcm or qr TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 17 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.3.6 burst mode operation (fbctrl pin) the flyback controller enters the burst mode when the output power is very low and the switching frequency is < 25 khz. in burst mode, the flyback converter switching frequency is 36.5 khz. the minimum flyback sense voltage of 232 mv, in combination with an offset voltage (see section 7.3.3 ), determines the peak current. a burst cycle starts when one of the following is made: ? v fbctrl >2.4v ? v cc TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 18 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.3.7 soft-start (fbsense pin) to prevent audible transformer noise during start-up, the soft-start function slowly increases the transformer peak current. place a capacitor c ss2 in parallel with resistor r ss2 (see figure 15 ) to implement the soft-start function. an internal current source charges the capacitor to: (5) with a maximum of 0.55 v. the start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of r ss2 and c ss2 . (6) the soft-start current i start(soft)fb switches on when v cc reaches v startup . when the v fbsense reaches 0.55 v, the flyback converter starts switching. the charging current i start(soft)fb flows when the v fbsense is < 0.55 v. if v fbsense exceeds 0.55 v, the soft-start current source starts limiting the current. after the flyback converter has started, the soft-start current source is switched off. when the ic is operating in the burst mode , the soft-start function is switched off. fig 14. burst mode operation aaa-002676 load v out fbctrl flyback active burst mode fbdriver 2.8 v 2.4 v 25 khz = flyback frequency 0.77 v vi start soft ?? fb r ss2 ? = ? soft s ? tart 3 r ss2 c ss2 ?? = TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 19 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.3.8 maximum on-time the flyback controller limits the on-time of the external mosfet to 38.5 ? s. when the on-time is longer than 38.5 ? s, the ic stops switching and enters the safe restart state. 7.3.9 overvoltage protection (fbaux pin) an output ovp is implemented in the greenc hip series. in the t ea1755t, the auxiliary voltage is sensed using the current flowing into the fbaux pin during the secondary stroke. the auxiliary winding voltage is a well-defined replica of the ou tput voltage. an internal filter averages voltage spikes. an internal up-down counter prevents false o vp detection which can occur during esd or lightning events. the internal counter counts up by one when the output voltage exceeds the ovp trip level within one switching cycle . the internal counter counts down by two when the output voltage has not exceeded the ovp trip level in one switching cycle. when the counter has reached six, the ic a ssumes a true overvoltage, sets the latched protection and switches off both converters. the converter only restarts after the ovp la tch is reset. in a typical application, the internal latch is reset when the vinsense voltage drops below 750 mv and is then raised to 860 mv. the latched protection is also reset by removing both the v cc and v hv . the demagnetization resistor, r fbaux sets the output voltage v o(ovp) at which the ovp function trips: (7) where n s is the number of secondary winding and n aux is the number of auxiliary winding of the transformer. current i ovp(fbaux) is internally trimmed. accurate ovp detection is made po ssible by adjusting the value of r fbaux to the turns ratio of the transformer. fig 15. flyback soft-start aaa-002677 soft start control ocp 10 fbsense s2 r ss2 c ss2 r sense2 2.1 a ocp level i start(soft)fb 7 a v oovp ?? n s n aux ---------- - i ovp fbaux ?? r fbaux v clamp fbaux ?? + ? ?? = TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 20 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 7.3.10 overcurrent protection (fbsense pin) the primary peak current in the transformer is measured accurately cycle-by-cycle using the external sense resistor r sense2 . the ocp circuit limits v fbsense to a level set by v fbctrl (see also section 7.3.3 ). the ocp detection is suppressed during the leading-edge blanking period, t leb (equals t on(fb)min ? t d(fbdriver) ), to prevent false triggering due to switch-on spikes. 7.3.11 overpower protection during the flyback converter primary stroke, the flyback converter input voltage is measured by sensing the current that is drawn from the fbaux pin. the current information is used to limit the maximum flyback converter peak current and is measured using th e fbsense pin. the internal com pensation is such, that a maximum output power is obtained which is al most independent of the input voltage. the opp curve is given in figure 17 . 7.3.12 driver (fbdriver pin) the driver circuit for the external power mosfet gate has a current sourcing capability of 500 ma at 2 v on the fbdriver pin and a curr ent sink capability of 1.2 a at 10 v on the fbdriver pin. these capabilities ensure fast switch-on and switch -off of the power mosfet for efficient operation. fig 16. ocp leading-edge blanking t leb ocp level v fbsense t 014aaa022 fig 17. overpower protection curve -360 0 -100 aaa-002678 545 400 i fbaux (a) v fbsense (mv) TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 21 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 8. limiting values [1] equivalent to discharging a 100 pf capacitor through a 1.5 k ? series resistor. table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit voltages v cc supply voltage ? 0.4 +38 v v latch voltage on pin latch current limited ? 0.4 +10 v v fbctrl voltage on pin fbctrl ? 0.4 +9 v v pfccomp voltage on pin pfccomp ? 0.4 +5 v v vinsense voltage on pin vinsense current limited ? 0.4 +10 v v vosense voltage on pin vosense current limited ? 0.4 +10 v v pfcaux voltage on pin pfcaux ? 25 +25 v v fbsense voltage on pin fbsense current limited ? 0.4 +5 v v pfcsense voltage on pin pfcsense current limited ? 0.4 +5 v v pfctimer voltage on pin pfctimer current limited ? 0.4 +10 v v hv voltage on pin hv ? 0.4 +650 v currents i fbctrl current on pin fbctrl ? 30 ma i fbaux current on pin fbaux ? 1+1ma i pfcsense current on pin pfcsense ? 1+10ma i fbsense current on pin fbsense ? 1+10ma i fbdriver current on pin fbdriver ? <10% ? 0.8 +2 a i pfcdriver current on pin pfcdriver ? <10% ? 0.8 +2 a i hv current on pin hv during start-up and restart -8ma ? = 3 % due to dv/dt on hv pin ? 15 +30 ma general p tot total power dissipation t amb <75 ? c-0 . 6w t stg storage temperature ? 55 +150 ?c t j junction temperature ? 40 +155 ?c esd v esd electrostatic discharge voltage human body model pins 1 to 14 [1] ? 22 kv pin 16 (hv) [1] ? 1.5 1.5 kv charged device model ? 500 500 v TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 22 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 9. thermal characteristics 10. characteristics table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to am bient in free air; jedec test board 127 k/w r th(j-c) thermal resistance from junction to case in free air; jedec test board 36 k/w table 5. characteristics t amb =25 ? c; v cc = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit start-up current source (hv pin) i hv current on pin hv v hv >75v v cc TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 24 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers v ton(pfccomp)zero zero on-time voltage on pin pfccomp 3.4 3.5 3.6 v pulse-width modulator pfc t on(pfc) pfc on-time v vinsense = 3.3 v; v vosense =2v; v pfccomp =v clamp(pfccomp) 1.8 2.8 3.8 ? s v vinsense =1v; v vosense =2v; v pfccomp =v clamp(pfccomp) 17 27 37 ? s output voltage sensing pfc (vosense pin) v th(start)vosense start threshold voltage on pin vosense open-loop 1.05 1.1 1.15 v v th(stop)vosense threshold stop voltage on pin vosense 0.95 1 1.05 v v hys(vosense) hysteresis voltage on pin vosense v th(start)vosense ? v th(stop)vosense 75 100 125 mv v reg(vosense) regulation voltage on pin vosense for i o(pfccomp) = 0 a 2.475 2.5 2.525 v v ovp(vosense) t on =0 ? s 2.59 2.62 2.65 v i bst(dual) dual boost current v vinsense TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 26 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers oscillator flyback f sw(fb)max maximum flyback switching frequency 110 130 150 khz v start(red)f frequency reduction start voltage transfer from dcm/qr to fr mode 3.8 4 4.2 v f sw(fb)swon(pfc) pfc switch-on flyback switching frequency 70 73 76 khz f sw(fb)swoff(pfc) pfc switch-off flyback switching frequency 50 53 56 khz f sw(fb)burst(ent) enter burst mode flyback switching frequency enter burst mode 21 25 29 khz f sw(fb)burst burst mode flyback switching frequency normal operation 31 36.5 42 khz v en(pfc)fbctrl pfc enable voltage on pin fbctrl override voltage 3.4 3.75 4.1 v peak current control flyback (fbctrl pin) v fbctrl voltage on pin fbctrl for maximum flyback peak current 4.6 4.9 5.2 v v to(fbctrl) time-out voltage on pin fbctrl enable voltage 5.3 5.5 5.7 v trip voltage 7.3 7.75 8.2 v v th(burst)off off-state burst mode threshold voltage on pin fbctrl 0.62 0.77 0.92 v v th(burst)on on-state burst mode threshold voltage on pin fbctrl 2.2 2.4 2.6 v v th(burst)exit exit burst mode threshold voltage on pin fbctrl 2.6 2.8 3 v v burst(exit-on) burst mode voltage difference between exit and on-state pin fbctrl = v th(burst)exit ? v th(burst)on 325 390 455 mv v burst(on-off) burst mode voltage difference between on-state and off-state pin fbctrl = v th(burst)on ? v th(burst)off 1.5 1.63 1.76 v r int(fbctrl) internal resistance on pin fbctrl 9.8 13.2 16.5 k ? i o(fbctrl) output current on pin fbctrl v fbctrl =0v ? 0.75 ? 0.6 ? 0.45 ma v fbctrl =4.5v ? 0.3 ? 0.24 ? 0.18 ma i to(fbctrl) time-out current on pin fbctrl v fbctrl =6v ? 35 ? 29 ? 23 ? a table 5. characteristics ?continued t amb =25 ? c; v cc = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 27 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers valley switching flyback (hv pin) (? v/ ? t) vrec(fb) flyback valley recognition voltage change with time [3] ? 75 - +75 v/ ? s t d(vrec-swon) valley recognition to switch-on delay time [3] -75 -ns soft-start flyback (fbsense pin) i start(soft)fb flyback soft start current ? 75 ? 60 ? 45 ? a v start(soft)fb flyback soft start voltage enable voltage 0.5 0.55 0.6 v overcurrent protection flyback (fbsense pin) v sense(fb)max maximum flyback sense voltage ? v/ ? t = 0 v/s 525 545 565 mv v sense(fb)min minimum flyback sense voltage ? v/ ? t = 0 v/s 221 232 243 mv t d(fbdriver) delay time on pin fbdriver v fbsense pulse-stepping 400 mv around v sense(fb)max -80 -ns t on(fb)min minimum flyback on-time v fbcrtl =3v; v fbsense = 0.75 v 280 340 400 ns i adj(fbsense) adjust current on pin fbsense ? 2.29 ? 2.1 ? 1.91 ? a overpower protection flyback (fbsense pin) v sense(fb)max maximum flyback sense voltage ? v/ ? t=0v/s i fbaux =80 ? a 525 545 565 mv i fbaux = 120 ? a 495 540 565 mv i fbaux = 240 ? a 400 445 490 mv i fbaux = 360 ? a 345 400 455 mv driver (fbdriver pin) i src(fbdriver) source current on pin fbdriver v fbdriver =2v - ? 0.5 - a i sink(fbdriver) sink current on pin fbdriver v fbdriver =2.5v - 0.7 - a v o(fbdriver)(max) maximum output voltage on pin fbdriver 10 11 12 v latch input (latch pin) v prot(latch) protection voltage on pin latch 469 494 519 mv i o(latch) output current on pin latch v prot(latch) TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 29 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 11. application information a power supply with the tea1755 t consists of a pfc circuit and a flyback converter (see figure 18 ). capacitor c vcc buffers the ic supply voltage. the ic supply voltage is powered using the high voltage rectified mains during start-up and the auxiliary winding of the flyback converter during operation. sense resistors r sense1 and r sense2 convert the current through the mosfets s1 and s2 into a vo ltage on the pfcsense and fbsense pins. the r sense1 and r sense2 values define the maximum pr imary peak current in mosfets s1 and s2. in the example, the latch pin is connected to a negative temperature coefficient (ntc) resistor. the protection is activated when t he resistance drops below a value as calculated in equation 8 : (8) a capacitor c timeout is connected to the fbctrl pin. r loop ensures that the time-out capacitor does not interfere with the normal regulation loop. r s1 and r s2 are added to prevent the soft-start capacitors from being charged during normal operation due to negative voltage spikes across the sense resistors. resistor r aux1 is added to protect the ic from damage during lightning events. r s3 and r comp are added to compensate for input voltage variations. the (stray) capacitance on the drain of mosfet s2 affects the frequency reduction slope and therefore, the pfc switch-on and switch-off levels. choosing the proper values for r s3 and r comp results in an input voltage independen t pfc switch-on and switch-off power level. r drv1 and r drv2 prevent the output drivers from being damaged due to, for example, power mosfet avalanche. in the application, the hv pin of the ic can either be connected to the center tap of the flyback transformer or to the drain of mosfet s2 refer to application note an11142 for more detailed information. v prot latch ?? i olatch ?? ------------------------------- 16.2 k ? TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 30 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers (1) in the application, the hv pin of the ic can either be connect ed to the center tap of the flyback transformer or to the drai n of mosfet s2. fig 18. TEA1755T typical application diagram 12 11 9 16 13 8 6 7 3 214 gnd latch v cc fbaux fbsense pfcdriver fbdriver pfcsense vosense hv pfcaux pfccomp vinsense fbctrl 10 4 1 5 pfctimer ic aaa-002624 tr2 d4 d3 c5 (1) c pfctimer r ntc c vcc s2 d 2 r4 r comp r s1 r5 s1 c ss1 r ss1 r sense1 r drv2 r drv1 r s2 r ss2 r s3 r sense2 r fbaux c ss2 c6 c bulk v out z1 tr1 r aux1 v mains c1 d1 r1 r2 r loop c timeout opto-feedback opto- feedback r3 c2 c4 c3 TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 31 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 12. package outline fig 19. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1 TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 32 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 13. revision history table 6. revision history document id release date data sheet status change notice supersedes TEA1755T v.1 20121025 product data sheet - - TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 33 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. 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[3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 14.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? 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TEA1755T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 25 october 2012 34 of 35 nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 14.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. greenchip ? is a trademark of nxp b.v. 15. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors TEA1755T hv start-up dcm/qr flyback and dcm/qr pfc controllers ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 25 october 2012 document identifier: TEA1755T please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 distinctive features . . . . . . . . . . . . . . . . . . . . . . 2 2.2 green features . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 pfc green features . . . . . . . . . . . . . . . . . . . . . 2 2.4 flyback green features . . . . . . . . . . . . . . . . . . . 2 2.5 protection features . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 general control . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.1.1 start-up and undervoltage lockout (uvlo) . . 5 7.1.2 power-down mode . . . . . . . . . . . . . . . . . . . . . . 7 7.1.3 supply management. . . . . . . . . . . . . . . . . . . . . 8 7.1.4 latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.1.5 fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.1.6 overtemperat ure protection . . . . . . . . . . . . . . . 8 7.2 power factor correction circuit . . . . . . . . . . . . . 8 7.2.1 t on control (pfccomp pin). . . . . . . . . . . . . . . . 8 7.2.2 valley switchin g and demagnetization (pfcaux pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2.3 frequency limitation . . . . . . . . . . . . . . . . . . . . . 9 7.2.4 mains voltage compensation (vinsense pin). 9 7.2.5 soft-start (pfcsense pin). . . . . . . . . . . . . . . . 9 7.2.6 pfc switch on/switch off control. . . . . . . . . . . 10 7.2.7 pfc switch off delay (pfctimer pin) . . . . . . 10 7.2.8 dual-boost pfc . . . . . . . . . . . . . . . . . . . . . . . 11 7.2.9 overcurrent protection (pfcsense pin) . . . . 12 7.2.10 mains undervoltage lockout/brownout protection (vinsense pin) . . . . . . . . . . . . . . 12 7.2.11 overvoltage protection (vosense pin) . . . . . 12 7.2.12 pfc open-loop protection (vosense pin) . . 12 7.2.13 driver (pfcdriver pin) . . . . . . . . . . . . . . . . 12 7.3 flyback controller . . . . . . . . . . . . . . . . . . . . . . 12 7.3.1 multimode operation . . . . . . . . . . . . . . . . . . . . 13 7.3.2 valley switching (hv pin) . . . . . . . . . . . . . . . . 14 7.3.3 current mode control (fbsense pin) . . . . . . 15 7.3.4 demagnetization (fbaux pin) . . . . . . . . . . . . 16 7.3.5 flyback control/time-out (fbctrl pin) . . . . . 16 7.3.6 burst mode operation (fbctrl pin) . . . . . . . 17 7.3.7 soft-start (fbsense pin) . . . . . . . . . . . . . . . . 18 7.3.8 maximum on-time . . . . . . . . . . . . . . . . . . . . . . 19 7.3.9 overvoltage protection (fbaux pin) . . . . . . . 19 7.3.10 overcurrent protection (fbsense pin) . . . . . 20 7.3.11 overpower protection. . . . . . . . . . . . . . . . . . . 20 7.3.12 driver (fbdriver pin) . . . . . . . . . . . . . . . . . 20 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 21 9 thermal characteristics . . . . . . . . . . . . . . . . . 22 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22 11 application information . . . . . . . . . . . . . . . . . 29 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 31 13 revision history . . . . . . . . . . . . . . . . . . . . . . . 32 14 legal information . . . . . . . . . . . . . . . . . . . . . . 33 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 33 14.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 34 15 contact information . . . . . . . . . . . . . . . . . . . . 34 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 |
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